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PSL

natg9

Can anybody help me understand how to use vunit in PSL

please explain the use with appropriate verilog file

 

i am using IFV tool to verify the design

 

thanks in advance

regards

Girish

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  • Hi Girish

    In case you're not aware of it, the Cadence tools like IUS and IFV now come with a really good documentation browser called "cdnshelp". If you run cdnshelp, it opens a GUI where you can search the docs for terms like "vunit".

    I'd recommend to read the IFV docs - look into the "book" called "Assertion Writing Guide" in cdnshelp, then navigate into "Using PSL", followed by "Placing PSL Assertions" and finally the section called "Putting PSL Assertions in Verification Units". This gives a lot of detail, but also a good overview on what to put in the vunit, the syntax and how the vunit binds to the design.

    In summary though, a vunit is a side-file that you compile along with your Verilog / VHDL source code. It effectively gets inserted into the module that it binds to, as though you'd typed the vunit code directly in the same module. This lets you access all the module's internal nets, and even add new Verilog code to assist the assertions (e.g. to decode a signal or count values).

    Note that you don't have to put your PSL inside comments in a vunit, since the compiler already knows to expect PSL keywords in the vunit.

    Hope this helps. Let us know if you need more help.

    Steve.

Reply

  • Hi Girish

    In case you're not aware of it, the Cadence tools like IUS and IFV now come with a really good documentation browser called "cdnshelp". If you run cdnshelp, it opens a GUI where you can search the docs for terms like "vunit".

    I'd recommend to read the IFV docs - look into the "book" called "Assertion Writing Guide" in cdnshelp, then navigate into "Using PSL", followed by "Placing PSL Assertions" and finally the section called "Putting PSL Assertions in Verification Units". This gives a lot of detail, but also a good overview on what to put in the vunit, the syntax and how the vunit binds to the design.

    In summary though, a vunit is a side-file that you compile along with your Verilog / VHDL source code. It effectively gets inserted into the module that it binds to, as though you'd typed the vunit code directly in the same module. This lets you access all the module's internal nets, and even add new Verilog code to assist the assertions (e.g. to decode a signal or count values).

    Note that you don't have to put your PSL inside comments in a vunit, since the compiler already knows to expect PSL keywords in the vunit.

    Hope this helps. Let us know if you need more help.

    Steve.

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