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lnternal error / Elaboration error ius81

Eder

 Hi,

When using ius, i'm getting this strange error

file: ./INCA_libs/irun.lnx86.08.10.nc/svpplib/tb.sv
                Caching library 'worklib' ....... Done
        Elaborating the design hierarchy:            
        Top level design units:                      
                tb                                   
        Building instance overlay tables: .................... Done
        Enabling instrumentation for coverage types: functional   
        Generating native compiled code:                          
                worklib.tb:sv <0x7a91fa59>                        
ncvlog_cg: *F,INTERR: INTERNAL ERROR
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
  TOOL: ncvlog_cg       08.10-s008
  HOSTNAME: linux-pzu3
  OPERATING SYSTEM: Linux 2.6.27.21-0.1-default #1 SMP 2009-03-31 14:50:44 +0200 x86_64
  MESSAGE: gq_cab_to_tab - not a CAB
-----------------------------------------------------------------
ncelab: *E,CUVCGF: Code generation for worklib.tb:sv <0x7a91fa59> failed.
ncelab: *F,CGFAIL: Code generation failed for one or more modules.
irun: *E,ELBERR: Error during elaboration (status 2), exiting.

 

I wonder if somebody could even get me some advices about that, or any hints do find the origins of this error. 

 

Parents

  •  Many thanks, TAM1.

    I was indeed trying to guess which module causes this error. Surprisingly, there are two modules that work out just fine when instrumented in isolation. But when they are instrumented in the same simulation, the error pops up. That's why I was thinking it might be a hierarchy-related problem.

    It seems I have no choice but sending Cadence the necessary setup.

     

Reply

  •  Many thanks, TAM1.

    I was indeed trying to guess which module causes this error. Surprisingly, there are two modules that work out just fine when instrumented in isolation. But when they are instrumented in the same simulation, the error pops up. That's why I was thinking it might be a hierarchy-related problem.

    It seems I have no choice but sending Cadence the necessary setup.

     

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