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Systemverilog SVA question: begin/end blocks

I hvae a question about property declarations. Is it legal to place them inside a begin/end block?

For example:

module my_module(
input logic clk,
input logic rstn,
...
);

begin : property_declarations
property p_reset_width( clk, rstn ); //negedge 'rstn' must be >= 3 cycles
@( posedge clk ) $fell( rstn )|=>$stable( rstn ) ##[*2];
endproperty
end : property_declarations

endmodule : my_module

Some tools are able to compile this module (as shown above), but other tools require me to remove the begin/end block.

tpylant over 16 years ago

Yes, that is supported with correct syntax. I don't think you want the '##' in the property.
Tim
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