Clock Generation in NC-VHDL & NC-VERILOG

Hi All,

We have clock generation block in one module. The actual code in VHDL is like this

VHDL  :::::::::

 Clk_1M_s_p : process
  begin
    Clk_1M_s <= '0';
    wait for 0.5 us ;
    Clk_1M_s <= '1';
    wait for 0.5 us ;
  end process Clk_1M_s_p;
 

VERILOG ::::::::::::::::

timescale 1fs/1fs

        always  begin : Clk_1M_s_p
                Clk_1M_s <= 'b0;
                #(0.5 * 1000_000_000) ; // MicroSeconds
                Clk_1M_s <=  1'b1;
                #(0.5 * 1000_000_000) ; // MicroSeconds
        end // Clk_1M_s_p;

When we have compared both the clocks in the Waveform in Simvison we are getting very minute difference which we cannot expand

through zoom options. When expanded through expancd-at time option. we found there is difference in event scheduling.

 Because of this generation, few events which depends on this clock is delayed and we are getting different results in VERILOG when compared to VHDL.

Thanks in Advance

Murali