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how to instantiate verilog module in vhdl top level

SUBBHAREDDY

Hi

I want to instantiate verilog module written in verilog.

Now my top level is vhdl.I want to instantiate inv.

Here below i had written simple verilog code :

`timescale 1ns/1ns
module INVERTER (IN, OUT);
output OUT;
input IN;
assign OUT = ~IN;
endmodule// INVERTER

Now want to simulate this verilog code in vhdl.

 How can i do it.

 Pls help me out to resolve this issue.

 

Thanks and regards

Subbhareddy

 

 

  • Hilmar

     Hi Subbhareddy,

     

    You can do that using component instantiation. I redid your inverter slightly to remove the VHDL in and out keywords:

     module inv(i,o);
    output o;
    input i;
    assign o = ~i;
    endmodule

     

    Then I wrote a tiny entity/architecture to use the module:

     

    entity e is
    end e;

    architecture a of e is
    component inv
    port (i: in bit; o: out bit);
    end component;

    signal my_in, my_out : bit;

    begin
    i : inv port map (i=>my_in,o=>my_out);
    end a;

     

    If you compile and elaborate it and start it up in ius/simvision, you'll see the inverter component instantiated in the architecture.

     

    Best regards,

    Hilmar

     

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