Community Functional Verification Systemverilog SVA reporting in IUS: how to suppress failures...

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Systemverilog SVA reporting in IUS: how to suppress failures caused by unfinished assertions?

cubicle82

I'm sure this is a frequently asked question (FAQ)

When we turn on SVA in our simulations, some of our long-running concurrent assertions are triggering failures at the end of the simulation.  It appears the assertion triggered, but the simulaiton $finish before the assertion had a chance to complete (either vacuously-succeed, or normal succeed.)

When the assetoin-report is issued, these 'dangling' assertions are classified as failures.

Is there a way to change the report, or change the assertion-behavior so dangling-assertions are not reported as failures?

Parents

  • In the 2012 version of the SVA LRM, the IEEE changed the default behavior of assertions to weak. The Incisive 13.2 release matches that change. By default, all SVA assertions start as weak. The SVA language added a keyword, "strong" to identify sequences that have to finish before the simulation ends.

     

    assert property ( @(posedge clk) $rose(request) |-> strong ( ##

  • grant ) );

     

    So if you can switch to 13.2, you can get the individual control that you are asking for.

Reply

  • In the 2012 version of the SVA LRM, the IEEE changed the default behavior of assertions to weak. The Incisive 13.2 release matches that change. By default, all SVA assertions start as weak. The SVA language added a keyword, "strong" to identify sequences that have to finish before the simulation ends.

     

    assert property ( @(posedge clk) $rose(request) |-> strong ( ##

  • grant ) );

     

    So if you can switch to 13.2, you can get the individual control that you are asking for.

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