Stats

  • Locked Locked
  • Replies 5
  • Subscribers 65
  • Views 18153
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Systemverilog SVA reporting in IUS: how to suppress failures caused by unfinished assertions?

cubicle82

I'm sure this is a frequently asked question (FAQ)

When we turn on SVA in our simulations, some of our long-running concurrent assertions are triggering failures at the end of the simulation.  It appears the assertion triggered, but the simulaiton $finish before the assertion had a chance to complete (either vacuously-succeed, or normal succeed.)

When the assetoin-report is issued, these 'dangling' assertions are classified as failures.

Is there a way to change the report, or change the assertion-behavior so dangling-assertions are not reported as failures?

Parents Reply Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.