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Inherit in PSL for VUNIT (IFV verification)

alexlop

 Hi,

I need an advise/suggestion.

I have a verilog module  which has N outputs of a specific protocol. I need to check that it generates the protocol correctly.

Can I write a VUNIT for a single output and then somehow instance this VUNIT (including binding it to an apropriate output wire) for each of the N outputs? (Instead of writing the same assertions N times)

Thank you!

P.S.

If you have other suggestions how to make it more simple, I would be glad to hear.

 

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