Systemverilog issues are not covered by Cadence.

Hi,
I would like to understand some points about Systemverilog cadence simulator implementation.
I noticed that SystemVerilog of Cadence (irun 64 - v 08.20-p001: ) does not implement or has different code styles from standard Systemverilog (example: Accellera's manual of Systemverilog has different points from systemverilog used in irun cadence. ).
I want to understand the Systemverilog, and I am following a lab from www.testbenches.in (verification of a switch).
However, when I compile and elaborate the Systemverilog using "irun", a lot of errors have been generated.

I could fixed the great number of errors and even mistakes. However, some issues keep opened such as undesirable behavior/mistakes or issues were not implemented in the irun.
I got the original code from www.testbenches.in. However, there is a case that I cannot fixed (case 4).

Let`s analyse these examples:
 
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*******************************
Example 1:
Original code from site www.testbenches.in.
////////////////////////////////////////////////
interface mem_interface(input bit clock);
  logic [7:0] mem_data;
  logic [1:0] mem_add;
  logic       mem_en;
  logic       mem_rd_wr;
 
  clocking cb@(posedge clock);
     default input #1 output #1;
     output     mem_data;
     output      mem_add;
     output mem_en;
     output mem_rd_wr;
  endclocking
 
  modport MEM(import cb.*,input clock);

endinterface
////////////////////////////////////////////////


In this interface, I need to modify the parameter of modport. The keyword import cb.* cause an error in the simulator. I have to replace import cb.* for clocking cb:

Modified code to run in the "irun":   modport MEM(clocking cb,input clock);



 
//mem_interface mem_intf(Clock); original interface;

To access any signal from interface, I have to modify the access way for each signal. For instance:
original code:  mem_intf.mem_rd_wr <= 0;  
to:             mem_intf.cb.mem_rd_wr <= 0; // I have to use ".cb." to access the internal signal of interface.



*******************************
*******************************
-------Example 2:
I could not instanciate an array of interfaces. The original code, the constructor "new" has an parameter that is 
an array of interfaces (virtual output_interface.OP output_intf_new[4]).  However, the irun rised an error.

original code:

function new(virtual mem_interface.MEM    mem_intf_new       ,
             virtual input_interface.IP  input_intf_new     ,
             virtual output_interface.OP output_intf_new[4] );

  this.mem_intf      = mem_intf_new    ;
  this.input_intf    = input_intf_new  ;
  this.output_intf   = output_intf_new ;
 
  endfunction : new

/////////////////////////////////////////////////////

Code modified: (this code works well)...
/////////////////////////////////////////////////////
class foo;
 //virtual output_interface.OP output_intf[3:0] ;
 
  virtual output_interface.OP output_intf_3 ;
  virtual output_interface.OP output_intf_2 ;
  virtual output_interface.OP output_intf_1 ;
  virtual output_interface.OP output_intf_0 ;

function new(virtual mem_interface.MEM    mem_intf_new       ,
             virtual input_interface.IP  input_intf_new     ,
             virtual output_interface.OP  output_intf_new_3,
             virtual output_interface.OP  output_intf_new_2,
             virtual output_interface.OP  output_intf_new_1,
             virtual output_interface.OP  output_intf_new_0);

  this.mem_intf      = mem_intf_new    ;
  this.input_intf    = input_intf_new  ;

  this.output_intf_3   = output_intf_new_3;
  this.output_intf_2   = output_intf_new_2;
  this.output_intf_1   = output_intf_new_1;
  this.output_intf_0   = output_intf_new_0;
 
 endfunction : new
///////////////////////////////////////////////////

I must instanciate four interfaces separately, because the constraint imposed by irun simulator.


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Example 3: ////////////////////////////////////////////////////////////////////////////
class Packet;
...
 rand byte data[];

  ----- >>constraint solve_size_length { solve data.size() before length; }  << ------
...
This example does not work. I tried to use data.size and the "solve ... before" construction does not work. "irun" has generated an syntax error.
What the suitable manner to use solve and before constructions using data.size?




*******************************
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------Example 4: //////////////////////////////////////////////////////////////
The example 4 presents the most important issue in this mail.  See the function called "byte_pack" below the constraints in the Packet class.
This function has as parameter a dynamic array passed by reference.
The "bytes" dynamic array is a stream of bytes from a packet.
 These fields are packed in this stream. However, when this function is performed, several results seem unpredictable.
As example of this behaviour is that fields length,da and sa are modified, violating the constraints (ex:  this constraint length_kind == GOOD_LENGTH) -> length == data.size(); 
happens rarely. )
When the function byte_pack is not performed (I commented it), all the constrains are meet.
The question is : how can I passed a array by reference? Is it possible in the cadence systemverilog simulator implamentation?

/////////////////////////////////////////////////////////////////////////
class Packet;
rand fcs_kind_t     fcs_kind;
rand length_kind_t  length_kind;

rand bit [7:0] length;
rand bit [7:0] da;
rand bit [7:0] sa;
rand byte data[];//Payload using Dynamic array,size is generated on the fly
rand byte fcs;

constraint address_c { da inside {`P0,`P1,`P2,`P3} ; }

constraint payload_size_c { data.size() inside { [1 : 255]};}

constraint length_kind_c {
   (length_kind == GOOD_LENGTH) -> length == data.size();
   (length_kind == BAD_LENGTH)  -> length == data.size() + 2 ; }

              
constraint fcs_kind_c {
   (fcs_kind == GOOD_FCS) -> fcs == 8'b0;
   (fcs_kind == BAD_FCS)  -> fcs == 8'b1; }

virtual function int unsigned byte_pack( ref logic [7:0] bytes[]);
  bytes = new[data.size() + 4];
  bytes[0] = da;
  bytes[1] = sa;
  bytes[2] = length;
  foreach(data[i])
  bytes[3 + i] = data[i];
  bytes[data.size() + 3] = cal_fcs();
  byte_pack = bytes.size();
endfunction : byte_pack
///////////////////////////////////////////////////////////////////////



Besides of that issues I mentioned, I am also writing this mail to know more about further versions of SystemVerilog simulator implementations will aggregate the all standard issues from Systemverilog.

I apologize for long text.

Thank you in advance.

Eduardo Wenzel Brião, PhD
Verification Engineer - CEITEC S.A. -
Porto Alegre, RS, Brazil