AXI eVC: How to set a master agent to be read-only

Hi,

I have an interconnect with two active master agents (IF0 and IF1), and two active slave agents (IF3 and IF4). Master IF0 cannot issue write transactions. My master sequence library has sequences that perform both write and read bursts. An example:

extend vr_axi_master_seq_kind : [ SEQUENCE_1 ];

extend SEQUENCE_1 vr_axi_master_seq {

    body() @driver.clock is only {

        do WRITE burst;

        do READ burst;

    };

};

I use the sequence in my test as:

extend MAIN vr_axi_master_seq {

    !sequence_1 : SEQUENCE_1 vr_axi_master_seq;

    body() @driver.clock is only {

        do sequence_1;

    };

};

The test will actually tell masters IF0 and IF1 to do the said sequence_1. How can I constrain such sequence to prevent

master IF0 from doing write bursts?