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  3. Simulation Problem : resolving X of a un-initialized f/f...

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Simulation Problem : resolving X of a un-initialized f/f whose output feedback to itself thru some logic

iclcle
iclcle over 16 years ago

Hi, there.

I'm trying to simulate post net, but a f/f cannot be initialized because of its initial state X.

The simulation goes like this :

(1) D of the flop = (A1&A2 ) | (B1&B2)  <= actually, this equation implemented with a complex gate (AO22)

(2) net A1 = Q of the flop, net B2 = ~Q of the flop

(3) when the flop is needed to be initialized, logic '1' is fed to net A2 and net B1

(4) simulator ( I'm using ncverilog ) calculates the D of flop as 'X', even if A2 & B1 is '1'

But, in real world, the Q of flop must be '0' or '1'... So, the D of flop must be '1' and the flop can be initialized.

 

Is there any solution to simulate this situation correctly ?

Currently, I'm using 'force' when the initialization condition detected. ( always block which check, force and release )

Does anybody have any suggestion ?

 

Thanks.

 

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  • StephenH
    StephenH over 16 years ago

    I feel your pain here, I've been in the same situation before. The problem is that the Verilog language defines how the simulator must resolve X and Z in logic equations. In some situations this can seem quite illogical as it contradicts what we as humans can deduce about the real-world behaviour! :-(

    The Verilog LRM (IEEE1364-2001 page 82, "truth tables for multiple input logic gates") specifies that an AND of X and 1 returns X. This makes sense if we look just at that one gate in isolation, we cannot say whether the output will be1 or 0. So in your RTL, both AND gates have a known-good 1 input (A2, B2) and an X input (Q, ~Q); thus both AND gates return X.

    The spec says for an OR or X with X, the output is X (can't argue with that!), hence your flop's D input will always see an X until the Q becomes known. Catch-22...

    If your A2 and B2 were both 0 for a clock cycle, the flop would initialise, becuase "0 & X" returns 0, letting the flop input get to a known state.

    It's a tricky one, because we can analyse the bigger picture and work out what would really happen, but the simulator is deliberately (by LRM specification) forced to take an event-driven "dumb" view of the design. If we enhanced the simulator to infer the intended behaviour, it would likely trip up someone else with some other design style, because the simulator would no longer be implementing the Verilog spec.

    Rather than hacking the force condition into the RTL, you could do it less obtrusively via ncsim's TCL interface:
    stop -create -condition {(#flop_init.a2 == 1) && (#flop_init.b1 == 1)} -continue -execute {force flop_init.q = 1 -release -keepvalue 10} -delbreak 1
    This might look a bit complicated, but it's not too bad really! :)
    The -condition {...} defines the logical operation to stop on; the # in front of the signal name tells TCL to look at the net's value.
    -continue tells ncsim not to stop at the user prompt, and -delbreak is an optional thing to delete the breakpoint after N ocurrences.
    -execute defines the command to run; here we set a force that will self-release after 10 time units, and -keepvalue means don't restore the X, just hold flop_init.q a the forced value until the next RTL assignment to q.

    Hope that helps!

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