Stats

  • Locked Locked
  • Replies 2
  • Subscribers 65
  • Views 13428
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Unresolved adater ERR_DID_NOT_FIND_ADAPTER

random

Hi

I have a mixed HDL environment with a vhdl testbench and i am trying to access an internal signal which is verilog.I am using ncsim with specman.

I constrained the agent() of the unit instance to verilog.

keep soft abc.._u.agent() == "verilog";

    Opening file for message: abc_testbench.elog
   *** Error: ERR_DID_NOT_FIND_ADAPTER: Unresolved adapter identification name 'Verilog'.
When you set this condition to a severity of WARNING or IGNORE, then
the NULL_SIM adapter is used instead.

 Is there any switch i need to use along with ncsim/ncelab to solve this problem?

Any help in resolving this is greatly appreciated.

  • Hi. There are a number of things that might be wrong here. I'll ask the most obvious ones here, but if you don't want to go into the gory details of your testbench in public, you might want to open a service request via http://sourcelink.cadence.com/ (this should normally get you a quicker response than using an open forum anyway).

    1. Are you using ports or tick accesses to link your e code to the VHDL / Verilog? Tick accesses have been deprecated for a long time now, but I do still see people using them, and they cause problems in a mixed-HDL environment.

    2. Did you regenerate the stubs file after adding the new connections? Usually you can get away without acorrect stubs file if binding to VHDL, but when you bind to Verilog, it becomes essential to generate a stubs file so that the simulator knows which signals Specman will access.

    3. Did you generate both Verilog and VHDL stubs files? Did you compile both and instantiate both in the simulation snapshot?

    4. When generating the stubs file, did you load all of the code that will access the Verilog / VHDL? I've seen users who simply do "specman -c 'write stubs -vhdl; write stubs -verilog '". This is next to useless, because it doesn't load the e code, so the list of signal connections is not known. This would be a better example: "specman -c 'load my_tb_config.e; write stubs -vhdl; write stubs -verilog'"

     5. Have you looked at the Specman documentation for doing mixed-HDL simulations? There is also a simple example that teaches you the right steps: $SPECMAN_HOME/examples/IES-XL/mixed/

    Cheers,
    Steve

  • Hi Steve

    Thanks for your reply. I had opened a ticket with Cadence support and got this issue resolved yesterday. The problem i had was that the agent() of sys was not constrained in our enviornment and this worked well in 5.XX version of specman but now when we migrated to the newest version, i  have to explicitly constrain agent() attribute of sys - in my case to "vhdl".

    I also wasn't loading specman module (present in specman.v) while ncelab. ( I missed this step.. Our prev environment was using modelsim and they used to load it while running vsim)

    I corrected these two errors and recreated stubs files. Now i can run sims without any errors.

     

    Regards

    Keerthi

     

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.