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NCsim and SystemVerilog issue

navis

 Hello all,

I have follow problem using SystemVerilog.

I'm writing some testbench. My test bench has some input and outputs ports. Thiese ports are delcared as a "logic". My class that handling this ports can't drive inputs and outputs. I beleive this ports should be interpreted as a global variables, and should be accessible by my class methods. But in practice this not happening.

 

Could someone have some ideas why this is happen.

 

Best regards and thanks

  • Does this represent what you are asking about:

    module tb(input logic in, output logic out);

    endmodule

    class a_c;
      bit a, b;
      function new();
        a = in;
        b = out;
      endfunction
    endclass

    Tim

     

  • BTW, this does work:

    module tb(input logic in, output logic out);

    class a_c;
      bit a, b;
      function new();
        a = 0;
        update();
      endfunction
      function void update();
        a   = in;
        b   = a;
        out = b;
      endfunction
    endclass

    a_c a = new();

    assign #1 in = ~out;

    always @(in) begin
        a.update();
    end

    initial begin
      $monitor($time,,in,,out);
      #10 $finish;
    end

    endmodule

    Tim

     

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