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VHDL source code encryption

PaulU

I'm in a situation where some IP written in VHDL must be sent to a customer so he can simulate it. Of course we don't want to send the source code.

Normally, what we do is sending pre-compiled libraries, where the the VHDL files are compiled using the -nodebug option of vcom. This is for ModelSim/QuestaSim.

Now we're facing a customer who does not use ModelSim. Instead, he uses a simulator by Cadence (Incisive, I suppose, or ncsim). We do not have Cadence tools.

So, what's the best way to cope with this?

The first question is whether ncvhdl has a similar option as the -nodebug option of vcom, hiding all internal signals and hierarchy. I have tried to find the manual pages of ncvhdl on www.cadence.com but the search results from that site are awful. Another question is whether I as a non-Cadence customer can compile VHDL using Cadence tools.

Second thought is using the new VHDL-2008 `PROTECT keyword and create encrypted VHDL that can be compiled at the customer site.. A data sheet on the Incisive simulator however does not mention any 2008 support. Is this correct?

 Are there other options?

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