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My first verification environment in SV

Hi all,

I am a new user of SystemVerilog and have been asked to develop a simple verification envirionment, wherein the DUT can be blank.

I have to concentrate on the generator, driver and interface blocks to start with. I started with writing classes for the mentioned blocks but I am not able to integrate interface with classes. Can someone help me out with this? And may be you could also share a short example so that i know what my environment shall look like

Thanks

Shalom B over 15 years ago

Use virtual interface variables.
Shalom
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Leo1008 over 15 years ago

Thanks. I'll try that out
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tpylant over 15 years ago

There is a utility that ships with Incisive called IVB (Incisive Verif Builder). It will generate the templates for the driver, monitor, including interfaces. It will also generate an example of how to instantiate it.

Tim
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Leo1008 over 15 years ago

Alright but from where do I get this utility called IVB??
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StephenH over 15 years ago

Leo1008 said:
Alright but from where do I get this utility called IVB??

Well, assuming that you are a Cadence customer (after all, you're on a Cadence forum, right?), then you can find IVB in the "IES" simulator package. For historical reasons it's located in the Specman sub-tree of the simulator installation, but it can generate SystemVerilog testbenches as well.
The exact command is "ivb". You can get tons of help using it if you start the docs via "cdnshelp" and search for "ivb".
Also, take a look at the examples that ship with OVM, e.g. the "xbus" example will show you how interfaces and virtual interfaces are used to connect to the DUT and the driver classes.
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Leo1008 over 15 years ago

I finally used virtual interface variables and everything worked fine.
Thank you Shalom and everyone else.
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212121 over 15 years ago

Visit my site: http://syswip.com/ You will find simple systemverilog testbench there. Thanks.
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