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integration verification

Hi,

I am new to the verification environment. I am having a little trouble understanding the integration verifiation environment. Can some one please explain with example how looking at the hardware module can I see which signals to verify?

Thankyou.

StephenH over 15 years ago

This is the same subject that was posted in the Functional Verification forum here: http://www.cadence.com/community/forums/T/13825.aspx
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AteInfochips over 5 years ago

I think this following insight will help to understand the verification environment: http://bit.ly/36CTMxE This piece represents a complete guide on system-on-chip functional verification in order to speed the whole process for faster time to market in the silicon industry.
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