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Running Specman with VCS simulator

MVSI

Hello!

 I am trying to run the Specman with VCS simulator but its giving error. I tried with sn_simulator_test.sh script.

 Error-[UCLI-121] Runtime Argument Error.
Argument -s is not supported anymore in this release, kindly move to UCLI.
The correct usage is 'simv -ucli [-i <tcl file>]'. Please provide -ucli
switch to runtime argument, to enable UCLI. 

I tried with -ucli option after that also it's giving error. 

Also, I need to run the Specman with VCS simulator having mixed HDL environment (VHDL DUT and Testbench Verilog). Is any version of specman supporting this?

 

Thanks!

Manish Verma 

  • Hi Manish.

    From the message in your post, it looks like Synopsys might have chosen to change the interface to VCS without telling Cadence, so you might want to take it up with them to ask why they're breaking backwards compatibility!

    You haven't said which Specman or VCS versions you're tyring to use, so there's not much we can do to help you without more information.

    I would also recommend that you file a support ticket at http://support.cadence.com/, as the proper support system will ensure you get your answer quickly.

    Have you looked in the Specman docs for information on lining VCS and Specman?

  • Hi Stephen,

    Thanks for the reply!

    I am using specman version 9.2 and synopsys version 2009.12-B1.

    I checked with the document also, I didn't find the document for Mixed HDL environment running with specman+VCS.

    I have written already to support.

    Thanks!

    Manish 

  • Hi Manish.

    Thanks for the clarification. I have passed the question on to the Specman team to see if they're aware of anything witht eh versions you mentioned.

    In the 9.2 Specman docs there is a section called "Using VCS with Specman" which details how to link the tools. I agree though that there's nothing obvious about Mixed-HDL simulation in VCS. To be honest it's almost 10 years since I last used VCS and back then I didn't try any mixed HDL so I can't help you there! Maybe when you find out you could post a summary in this thread so that the other forum users can benefit from your experience?

    Regards,

    Steve.

  • Hi Mainsh,

     - Specman is currently support only vcs2008 stream. It is not support VCS 2009.12-B1.

    sn9.2 update release will add the support for 2009.06.

    -  You can work with UCLI but this option will not always work for you - we are working with Synopsys to add the support for UCLI in the coming hot fix of 9.2.

    - you can work with MIXED design , this is not documented in specman documentation since Synopsys develop and support this option.

    Here is an example of typical flow in a mixed environment:

    %specman -c "load <e-file>; write stubs -verilog"
    %vlogan -q <verilog-file> specman.v
    %vhdlan -nc $VCS_HOME/packages/synopsys/src/specman.vhd
    %vhdlan -nc <vhdl-files>


    %sn_compile.sh -sim vcs -sim_flags "-debug test specman specman_wave"

    - This will create "vcs_specman" executable:

    - You must set the SPECMAN_VCSMX_VHDL_ADAPTER environment variable: SPECMAN_VCSMX_VHDL_ADAPTER=$VCS_HOME/linux/lib/libvhdl_sn_adapter.so

    Regards,

    Michal

     
  • Hi Michal, Thanks for the reply! I tried these commands but still I am getting the error that ERR_DID_NOT_FIND_ADAPTER. for VHDL. Regards, Manish
  • Sorry for the previous reply, actually the error given was: “ **** Error: From VCS adapter: The external port ‘sys.xor_top.xor.p_clk’ has an invalid hdl_path() specified as ‘xor_top.xor_try.clk’. The signal name does not exist.” I am using the xor mixed hdl code which came with cadence installation. Regards, Manish

  •  Can you please try to compile with -sim vcssv ?(sn_compile.sh -sim vcssv -sim_flags"-debug -lca xor_top specman ")

    Thanks,

    Michal

  • Hi Michal, I used your suggestion but it's giving error for specman.v didn't found. I think it's problem with synopsys adapter, i am in contact with synopsys support. I will let you know if I will get the solution. Regards, Manish

  •  This is the flow when using -sim vcssv

     specman -c "load <e-file>; write stub -vcssv";

    vhdlan -nc $VCS_HOME/packages/synopsys/src/specman.vhd
    vhdlan -nc  <other vhdl -files>
    vlogan <verilog files> specman.sv -sverilog
    sn_compile.sh -sim vcssv -sim_flags " -sverilog -lca -debug <top> specman"
     

    The problem is not with synopsys adapter - it some bug in Specman verilog adapter that will be fixed in next version.

    This is the reason I asked you to use the SystemVerilog adpater.

    Please give it another try.

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