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Toggle coverage on SystemVerilog interfaces

maxb

In our design we use interfaces to connect modules. But when running coverage analysis, all signals in the interfaces show 0% toggle coverage, although the signals are clearly toggling in the simulation. How do I get the correct toggle coverage?

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  • Hi Max,

    Toggle coverage is not yet supported for SV interfaces. If you email me your contact inf, I can be sure to notify you when support is added.  My email is nlin@cadence.com.

     In the future, if you have questions about the functionality of the tools, be sure to go to support.cadence.com

    Best Regards,

    Nancy

Reply

  • Hi Max,

    Toggle coverage is not yet supported for SV interfaces. If you email me your contact inf, I can be sure to notify you when support is added.  My email is nlin@cadence.com.

     In the future, if you have questions about the functionality of the tools, be sure to go to support.cadence.com

    Best Regards,

    Nancy

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