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Event ordering in SV and Verilog

Hi,

I read that the event ordering is better in SV.In what ways is it better.I see that the program block execution in which we usually write the testcase occurs in the reactive region ,after the blocking and non-blocking assignments have been evaluated and assigned ,which is a good feature ,How is that so? Would races in asignmentaffect the testcase?

Regards,

Pooja Vaishnav

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