Usage of verilog compiler directive in TCL

I think we're confusing each other with the terminology! :-)

You initially asked about `defines, such as:
    `define BUS_WIDTH 32
These cannot (as far as I know) be seen from TCL.

 When I said parameters, I specifically meant Verilog parameters, such as:
  module foo (...);
    parameter BUS_WIDTH = `BUS_WIDTH;

These ARE accesible from TCL, so you can do things like:
  ncsim> describe tb.dut.BUS_WIDTH
And ncsim will tell you the value as a text string that you can manipulate in TCL.

Does that help clarify things?

Hi StephenH,

I tried using following command in ncsim:
ncsim> describe tb.dut.BUS_WIDTH

And I am getting following result:
tb.dut.BUS_WIDTH...parameter logic [31:0] = 32'h00000001

I want to assign this value to tcl variable. Do you know how to assign it?
I have tried following:

set prm_bus tb.dut.BUS_WIDTH

But when I print the value using
puts $prm_bus
It prints tb.dut.BUS_WIDTH, not 1.

Hi StephenH,

I tried using following command in ncsim:
ncsim> describe tb.dut.BUS_WIDTH

And I am getting following result:
tb.dut.BUS_WIDTH...parameter logic [31:0] = 32'h00000001

I want to assign this value to tcl variable. Do you know how to assign it?
I have tried following:

set prm_bus tb.dut.BUS_WIDTH

But when I print the value using
puts $prm_bus
It prints tb.dut.BUS_WIDTH, not 1.