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Usage of verilog compiler directive in TCL

usiciliani

I'm using TCL scripts to stimulate a verilog database (based on task - schedule statement).

Is there a way to use verilog compiler directive (like `define) in TCL?

Parents

  •  I don't think there's a way to do this directly. Normally you would use the TCL command "describe" to get information on a simulation object (net, module, class etc).However, a `define is a compiler macro, and in Verilog isused as a simple text substitution.
    Thus by the time the simulator ges to execute the code, it doesn't really have any idea that the macro even exists, it will have been substituted for some text long before.

    I am loathe to recommend doing any kind of etstbench in TCL when there are so many better ways to do it.
    Still, if you really must use TCL, then I would recommend that you extend your Verilog testbench, and copy the important `define values into some parameters or other such object that can be used with the describe command.

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  •  I don't think there's a way to do this directly. Normally you would use the TCL command "describe" to get information on a simulation object (net, module, class etc).However, a `define is a compiler macro, and in Verilog isused as a simple text substitution.
    Thus by the time the simulator ges to execute the code, it doesn't really have any idea that the macro even exists, it will have been substituted for some text long before.

    I am loathe to recommend doing any kind of etstbench in TCL when there are so many better ways to do it.
    Still, if you really must use TCL, then I would recommend that you extend your Verilog testbench, and copy the important `define values into some parameters or other such object that can be used with the describe command.

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