Sparse memory support

 Hi Abhishek,

The best solution for you would likely be vr_ad.It is a very powerful package for register and (sparse) memory modelling.You can find it in either your icpm install, or the sockit, where it is packaged nowadays.

Thanks,

Hilmar

Hi Abhishek

Did you implement the 4GB memory using sparse memory or by any other means. I am also looking for a similar kind of implementation. It will be helpful if you share some info on this.

Thanks in advance

Regards
Arun Prasad

 Hello,

 Simple way is to use 'Associative arrays' from System Verilog.

 Else if you need more advanced one then go for 'regmem package'.

http://www.ovmworld.org/contributions-details.php?id=43&keywords=An_OVM_Register_Package_V_2.0

Regards,

Abhishek

The simplest way to model a very very large memory in Verilog is to use the Cadence "sparse" pragma. Here's a snippet from the Cadence documentation:

To declare a sparse array, insert the /*sparse*/ pragma anywhere within the declaration of the array or after the semicolon that ends the array declaration. For example:

reg [31:0] /*sparse*/ mem [0:3000000];

reg [31:0] mem /*sparse*/ [0:3000000];

reg [31:0] mem [0:3000000]; /*sparse*/

thanks abhishek :)

thanks TAM1