explenation on the verilog_wire() method

Hi Eyal,

I'm not sure where you looked in the docs so I'm not sure what exactly you don't understand.

I'll try to explain.

To drive Verilog wires you should do the following:

1. Define and bind a simple external out or inout port to drive the Verilog wire.

2. Set either verilog_wire() to TRUE or driver() to TRUE.
If neither verilog_wire() nor driver() is set to TRUE, Specman assumes that the Verilog object is a register.
The main difference between verilog_wire() and driver() is this:

verilog_wire() merges all of the ports that have this attribute into a single Verilog driver.
driver() creates a separate driver for each port.

Here is an example:

verilog definition:

wire [31:0] data_bus;

in e:

data : inout simple_port of uint is instance;
keep bind(data, external);
keep data.hdl_path() == "data_bus";
keep data.declared_range() == "[31:0]";-- for bus, specify range
keep data.verilog_wire() == TRUE; -- to drive a Verilog wire

Hope this clarifies. 

Semadar

I guess if you want to drive any verilog wire from e, you need to define verilog_wire() to TRUE. If it is not defined, Specman simply “deposits” a value on he wire at the end of the time-step, overwriting values driven by the imulator at that time. Deposited values can be changed by the simulator at he next simulation time-step by any other HDL/e drivers.

This option is a must for non-cadence simulator. For cadence simulator, it is required only when verilog wire is driven by HDL as well as e. For cadence simulator, if verilog wire is driven only by e, verilog_wire() is optional.

Thanks,
Sandeep
http://digitalverification.blogspot.com