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encryption of source files

vmark

Hi all. I have a question about encrypting the source files in verilog or VHDL:

 

1) Besides encryption which prevents the source code to be visible, is there any way to somehow limit the encrypted files to be used (in simulation) only on one machine? (For example, based on some compute's or work station's ID)

 

2) Is there any way to set an evaluation period for the encrypted files after which they cannot be used (in simulations)?

 

Thanks in advance.

  • This seems to have been moved into the Custom IC Design Forum, which I don't think is the right place for it. I'll move it to the Functional verification forum.

    I don't think what you're after is possible - it would be worth checking the ncprotect documentation.

    You can use a public/private key pair, which can restrict things somewhat, but I don't think you can lock it to a particular machine or for a particular duration. Perhaps an Incisive expert knows better... (I am not an Incisive expert).

    Regards,

    Andrew.

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