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Stubs in E language

Raviram80

Hi All,

 Can someone please explain what does stubs mean in specman.They are used to interact with the DUT, how?. They are written in verilog.

 I am not completey sure after reading from a book.

 Thanks,

 

  • Raviram80

    Can someone please reply. this is urgent.

  • StephenH

    If it's urgent, then you should file a service request at http://support.cadence.com/, rather than relying on a public forum.

    Depending on when you came into design and verification, you may recall the days where simulators needed stub wrappers for instantiating VHDL in Verilog and vice-versa. Specman stubs are similar in concept.

    Stubs are not always Verilog, if you look in the docs you'll see there are options for whatever simulated design language you're using.

     

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