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Assertions

Raviram80

Hi All,

 

Can someone provide me with a link explaining assertions.

 One question if we have to  use assertions in Specman, will they have to be coded first in system verilog and then called in e code

 Thanks

  • StephenH
    Specman does not depend on inferior languages like SystemVerilog, it has its own assertion capability built in to the language.
    Look up "expect" or "temoral expressions" in the Specman docs. The docs also have quite a lot of information on how to use and write assertions, including an "english to temporal dictionary" that helps you translate from english statements about the design into assertions.
  • Raviram80

    Stephen,

     Thanks a lot for answering all my questions

     

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