Elaborate Verilog and VHDL mixed language design

 I have VHDL design files and my top module is in Verilog.

i am using this command to compile and elaborate the design

    ncvhdl -work work -messages gate_10.vhd
    ncvhdl -work work -messages dff.vhd  
    ncvlog -work work -messages lfsr_gate_mixed1.v   
    ncvlog -work work -messages lfsr_tb1.v

    ncelab -work work -messages -access +rwc +mixedlang work.lfsr_tb1

when i try to elaborate the design i get this error 

ncelab: *E,CUVMUR (./lfsr_gate_mixed1.v,9|6): instance 'lfsr_tb1.L1@lfsr_gate_mixed1<module>.D1' of design unit 'dff1' is unresolved in 'work.lfsr_gate_mixed1:module'.

ncelab: *W,CUDEFB: default binding occurred for component instance (lfsr_tb1.L1@lfsr_gate_mixed1<module>.G1) with design unit (WORK.GATE_10:GATE10_ARCH).

 what am i doing wrong??