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MixedLanguage (Verilog+VHDL) Question

ashfaqh

 Hello:

 I am using  ncsim   09.20-s016.

 I have a VHDL DUT.  The testbench top level is VHDL.  But, I have a few Verilog modules in the testbench.

From one of the Verilog modules, I want to access (monitor) a signal inside the DUT (VHDL). 

For example,

if (top.level_1.level_2.sigout_1 == 1'b1) 
            $display("Posedge received at time: %d", $time) ;

 I get the following error:

 ncelab: *E,CUVHNF (...): Hierarchical name component lookup failed at 'top'.

 

1.  Is it not possible to monitor a signal  inside a VHDL block from a Verilog module?

 

Thanks.

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