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MixedLanguage (Verilog+VHDL) Question

ashfaqh

 Hello:

 I am using  ncsim   09.20-s016.

 I have a VHDL DUT.  The testbench top level is VHDL.  But, I have a few Verilog modules in the testbench.

From one of the Verilog modules, I want to access (monitor) a signal inside the DUT (VHDL). 

For example,

if (top.level_1.level_2.sigout_1 == 1'b1) 
            $display("Posedge received at time: %d", $time) ;

 I get the following error:

 ncelab: *E,CUVHNF (...): Hierarchical name component lookup failed at 'top'.

 

1.  Is it not possible to monitor a signal  inside a VHDL block from a Verilog module?

 

Thanks.

Parents
  • Hello, If the top instance is vhdl the path should begin with a ":". With that in mind try (:top.level_1.level_2.sigout_1 == 1'b1). btw if you want to know the correct path to the object, you can comment out the problem code and go ahead and compile/elab/simulate in gui mode. when in the gui choose the sigout_1 signal from any of the simvision windows. then right mouse button and choose the describe option from the menu. The result will be the correct path to the object that should be used in the code. Hope that helps. Mickey
Reply
  • Hello, If the top instance is vhdl the path should begin with a ":". With that in mind try (:top.level_1.level_2.sigout_1 == 1'b1). btw if you want to know the correct path to the object, you can comment out the problem code and go ahead and compile/elab/simulate in gui mode. when in the gui choose the sigout_1 signal from any of the simvision windows. then right mouse button and choose the describe option from the menu. The result will be the correct path to the object that should be used in the code. Hope that helps. Mickey
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