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MixedLanguage (Verilog+VHDL) Question

ashfaqh

 Hello:

 I am using  ncsim   09.20-s016.

 I have a VHDL DUT.  The testbench top level is VHDL.  But, I have a few Verilog modules in the testbench.

From one of the Verilog modules, I want to access (monitor) a signal inside the DUT (VHDL). 

For example,

if (top.level_1.level_2.sigout_1 == 1'b1) 
            $display("Posedge received at time: %d", $time) ;

 I get the following error:

 ncelab: *E,CUVHNF (...): Hierarchical name component lookup failed at 'top'.

 

1.  Is it not possible to monitor a signal  inside a VHDL block from a Verilog module?

 

Thanks.

Parents

  • Mickey:

    Your suggestion has worked very nicely!  Thank you very much for your help. 

    I wasn't aware of the $nc_mirror() task which allows VHDL signals to be probed from Verilog module.  

    I also successfully experimented by calling a user-defined Verilog task() from a verilog island module inside a VHDL top-level DUT -- that also works fine.

     For example, expanding on your example, the t_write() task call inside the island verilog module executes correctly in ncsim.

    Thanks again.

    -ashfaqh

     

    reg my_probe;

    initial

         $nc_mirror ("my_probe", ":top.level_1.level_2.sigout_1");    // sigout_1 is a VHDL signal

    always @(posedge my_probe)

       begin

            $display("my_probe asserted high at time: %d", $time) ;
            top_vhdl_level.vhdl_level_2.vhdl_level_3.verilog_module.t_write() ;    // t_write() is task inside verilog module

       end

     

Reply

  • Mickey:

    Your suggestion has worked very nicely!  Thank you very much for your help. 

    I wasn't aware of the $nc_mirror() task which allows VHDL signals to be probed from Verilog module.  

    I also successfully experimented by calling a user-defined Verilog task() from a verilog island module inside a VHDL top-level DUT -- that also works fine.

     For example, expanding on your example, the t_write() task call inside the island verilog module executes correctly in ncsim.

    Thanks again.

    -ashfaqh

     

    reg my_probe;

    initial

         $nc_mirror ("my_probe", ":top.level_1.level_2.sigout_1");    // sigout_1 is a VHDL signal

    always @(posedge my_probe)

       begin

            $display("my_probe asserted high at time: %d", $time) ;
            top_vhdl_level.vhdl_level_2.vhdl_level_3.verilog_module.t_write() ;    // t_write() is task inside verilog module

       end

     

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