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Write, compile and simulate verilog/vhdl code in cadence

Sambhav

Hi,

I want to use cadence to write my verilog/vhdl code, compile and simulate the same.

Can i get some help or some kind of tutorial for the same. For instance, what tools do i use etc.. I saw something like NC-verilog and Verilog-XL etc but i have no idea how to use them..

 

Thanks,

Sambhav

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