looking for advise on connecting to analog model

 Hi all

I am looking for advise on the next issue :

i verifiing a  digital design that is coneccted to an analog one , for simulation i was supplied by a vhdl behavioral model of the analog part.

i want to create a loopback in the simulation meaning to sample the output of the analog model which is of type real and after some delay to inject it (with some modification) back to the model input which is of type real as well.

i am using specman 9.2 and my questions are:

1) is there a in/out simple_port of real ?

2) can i use list of real ?

3) do you reccomend on others way to do so not with specman (in the test banch maybe) ?

thanks Eyal.