event on combination of VHDL and verilog RTL path

Hi All, I am making one event like : event collect_cover_done_e is rise('~/ve_top_tb_sn.DUT.ve_core_inst.pss_top_inst.pss_ring_inst.pss_core_inst.pss_arcss_core_inst.ipss_dma.done_w')@sim; Here the issue i am getting is : *** Error: From NCVHDL adapter: Missing access rights. No read/write access rights were specified for the VHDL signal ':DUT:ve_core_inst:pss_top_inst:pss_ring_inst:pss_core_inst:pss_arcss_core_inst:ipss_dma:done_w' accessible from Specman. This is because i hope my testbench is in VHDL and the path which i am accessing at the last is verilog.. Basically our RTL is combination of VHDL and verilog. Please let me know what is the issue over here. Thanks