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How to preload a memory in a design using Tcl scripts in NCSIM

Arrun

I have to verify DMA transfer between two memories present in my design. For example consider there is L1 & L2 cache memories are present in the design. I have transfer 100KB (kilobytes) of data from L1 to L2 by configuring DMA.

 For the above scenario i have to preload the L1 memory so that simulation time can be reduced otherwise if i write from test cases using DSP it will take so much time to write 100 kilobytes to L1.

We are using Cadence NCSIM for simulation. Is there any option present in NCSIM to preload the memory using some Tcl scripts.

 Expecting for some good reply

Parents

  • The TCL memory command loads a Verilog or VHDL memory from a memory file or dumps the contents of a specified memory object to a specified memory file. The command has two modifiers: -load and -dump.

    ParagraphBullet
    		Use the -load modifier to load memory from a memory file.
    ParagraphBullet
    		Use the -dump modifier to dump the contents of memory to a memory file.

    Check out the Incisive Simulator Tcl Command Reference for more information about the command and file syntax.

    Tim

Reply

  • The TCL memory command loads a Verilog or VHDL memory from a memory file or dumps the contents of a specified memory object to a specified memory file. The command has two modifiers: -load and -dump.

    ParagraphBullet
    		Use the -load modifier to load memory from a memory file.
    ParagraphBullet
    		Use the -dump modifier to dump the contents of memory to a memory file.

    Check out the Incisive Simulator Tcl Command Reference for more information about the command and file syntax.

    Tim

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