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System Verilog rule file for HAL

diablo

hi all, 

I apoligize if my question is not relevant to this forum. I am using HAL for linting which comes with Cadence INCISIV 10.2. We  do  RTL design using system verilog construct. I looked at default built in rules for HAL. It has rules for only VERILOG and VHDL. Most of the verilog rules apply to system verilog as well, but there are numerous feature in system verilog which is shown as an error while linting via HAL. Is there a way to include system verilog rule? or is it not supported yet? Thanks for your time and help. 

  • HI,

        In the INCISIV 10.2 there are already built in rules for the systemverilog but not fully still need to be enchanced , for the list of supported systemverilog constructs you can refer the hal.pdf in your installation path in the pdf at page num 149 you can find the complete list of both supported and un-supported constructs.

     

    Thanks

    Srikanth M.

  •  Thanks Srikanth for the info. I did find the list of systemverilog construct, it was helpful. While going through the default rule file using "haldefedit", i found rules definition distinctly for Verilog and VHDL and even mixed language. Are these systemverilog supported construct rule check are defined within Verilog rule definition? i was wondering whether there was a separate 'System Verilog" rule check i can incorporate in default hal rule file.

     

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