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forcing a netlist path

Ravisinha
Hi, I have to force some signals inside netlist. When i see that signal full path in design browser i found that ":DUT:ve_core_inst:pss_top_inst:pss_top_inst.pss_ring_inst.pss_core_inst.pss_arcss_core_inst.ipss_cpu_isle.ipss_arc_ram_blk.iccm_memX12XXiccm_mem_8kXipss_iccm_rams.\U_pss_wrapper_iccm8kx32_int/U_pssram8192x32 .u0.PreloadFilename" Basically a mixture of ".(dot)" and "/". But if i use the same path to use for force its giving an error that path is not found. Can anyone let me know what is the issue ? Thanks
  • Sorry the path was wrong pasted in above post.. the actual path is like : :DUT:ve_core_inst:pss_top_inst:pss_top_inst.pss_ring_inst.pss_core_inst.pss_arcss_core_inst.ipss_cpu_isle.ipss_arc_ram_blk.iccm_memX12XXiccm_mem_8kXipss_iccm_rams.\U_pss_wrapper_iccm8kx32_int/U_pssram8192x32 .u0.PreloadFilename

  • Hi Ravisinha,

    That is happening because of the flattened netlist format (from the synthesis tool). So better to align with the synthesis tool's format instead of the NCSim format. (instead of ":" try with the "/").

     

    Thanks,

    Paul

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