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write a single assertions with constraints embedded

Ashish Goel

 My specs say that PLL should fire a loss of lock interrupt within 8 clock cycles for loss of lock condition in non-bypass mode

 

Now i have one assertion  which states loss of lock interrupt comes with 8 clock cycle w.r.t loss of lock condition 

constraint is that we should be non bypass mode 

 

Is it good way to pass the constraint in disable iff or there is some better way to acheive the same ?

 

 

  • It depends on what your spec says. If the bypass mode can cancel the interrupt on any cycle then the disable iff clause is the right way to go. However if the interrupt comes after the lock is lost in non-bypass mode, and is not cancelled if you subsequently move to bypass mode, then the bypass mode should be factored into the trigger of the assertion.

    assert property (
      @(posedge clk)
      (~lock && ~bypass) |=> (1'b1 ##8 interrupt)
    );

     

  • Thankx StephenH 

    As per my requirement, disable iff is the option.

     Disable iff is good idea if the constraint are simple as in given case.

    Point a)

    ======

    If we have a complex constraint like bypass mode should be high for atleast 3 cycles to make sure that we have enter the bypass mode. then how can we include in the single assertion

    Don't you think it is better if we could link any constraint with an assertion by some construct.  

     point b)

    ======

    w.r.t. IFV can you throw some light on time taken to prove with two options 

     assert property (
      @(posedge clk)
      (~lock && ~bypass) |=> interrupt);

     assert property (
      @(posedge clk) disable iff (bypass)
      ~lock |=> interrupt);

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