Is there anyway that I can include a digital vector file in a verilog netlist file?
Are you talking about a file with each line representing a vector? For that you can use the readmem task to read it into a memory and then clock it out as needed.
Hello again and thanks for your assistance!
I would like to use Encounter to calculate power dissipation. Is it possible to use the verilog netlist generated for the Virtuoso schematic as the input file??? If not, how can this be accomplished? My layout is not being generated by Encounters synthesis tool, I'm using Virtuoso.