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dependecy checking ----- Can anybody tell me how to approach for this problem

Ashish Goel

 I want to check that none of the internal register in the design except error register is effected by the error condition on the inputs.

Simulation can check that error register is set for the error condition but it cannot check that none of the other register is effected by it.  Random simulation might be inefficient to propagate this change to the checker. As far as my thought process goes we cannot have any cover statement associated with it 

IFV also is not capable of check it 

Please advice 

  • If you're using UVM_REG or some other register shadowing checker. You can compare all the other registers for their known values (preferably using backdoor access). If you always check the full register space for correctness, you won't need a special coverage to indicate that. If such checking is a configurable option, you could condition the cover bin on that being set (so you only generate coverage for error bit and no register corruption).

  • I agree with your suggestion but we don't do it generally. Do we have any way of formal way of checking it  

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