I have a Testbench with a DUT which has VHDL and Verilog RTL modules. The tb_top is verilog. The test file is a verilog.
From the verilog test, I need to force a signal inside the DUT several hierarchies down.
The signal I need to force is inside a VHDL module. This signal is not available at the top level.
How do I do it?
I am using ncverilog/ncvhdl/irun version of 9.2.
Any suggestions with some simple code example is going to be very helpful.
You need to use $nc_force to force a vhdl down in the design hierarchy from a verilog testbench. It's fairly simple.
$nc_force ("source", "value", "after_time", "rel_time", "repeat_time", "cancel_time", "verbose");
for example, $nc_force (path.to.r1, "'1'", "verbose");
above example will force a '1' value (note that vhdl notation is used for the value to be assigned, if the destination was verilog you would use 1'b1) onto the hierarchical location, path.to.r1. Additionally verbose is included to have the tools output a message to stdout when the code is encountered during simulation.
If you would like more information regarding the other options, go to support.cadence.com and do a search using $nc_force as the search term.