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Forcing a VHDL signal from a Verilog Test/Env

ashfaqh

 I have a Testbench with a DUT which has VHDL and Verilog RTL modules.  The tb_top is verilog.  The test file is a verilog.  

 From the verilog test, I need to force a signal inside the DUT several hierarchies down.

 The signal I need to force is inside a VHDL module.   This signal is not available at the top level.

 How do I do it?

 I am using ncverilog/ncvhdl/irun version of 9.2.

 Any suggestions with some simple code example is going to be very helpful. 

 Thanks, 

 -Ashfaq Hossain 

Parents

  • Mickey:

     Thanks for your response.  I tried and got the following error msg.  Please suggest.

     Thanks,

     -Ashfaq

     

     Top level design units:
                    $unit_0x22e511b2
                    tb_test
              $nc_force(tb_test.u_tb_controller.u_hier1_top.hier2.hier3.hier4.hier5.signal_name[3], "'1'", "verbose") ;
                                                                                                                                                 |
    ncelab: *E,CUIOCP (./testbench/tb_test.v,109|141): Out-of-module reference terminating in a VHDL scope is not allowed (tb_test.u_tb_controller.u_hier1_top.hier2.hier3.hier4.hier5.signal_name[3]).
    ncelab: Memory Usage - 20.8M program + 170.3M data = 191.1M total
    ncelab: CPU Usage - 0.2s system + 1.2s user = 1.4s total (3.6s, 38.2% cpu)
    irun: *E,ELBERR: Error during elaboration (status 1), exiting.

Reply

  • Mickey:

     Thanks for your response.  I tried and got the following error msg.  Please suggest.

     Thanks,

     -Ashfaq

     

     Top level design units:
                    $unit_0x22e511b2
                    tb_test
              $nc_force(tb_test.u_tb_controller.u_hier1_top.hier2.hier3.hier4.hier5.signal_name[3], "'1'", "verbose") ;
                                                                                                                                                 |
    ncelab: *E,CUIOCP (./testbench/tb_test.v,109|141): Out-of-module reference terminating in a VHDL scope is not allowed (tb_test.u_tb_controller.u_hier1_top.hier2.hier3.hier4.hier5.signal_name[3]).
    ncelab: Memory Usage - 20.8M program + 170.3M data = 191.1M total
    ncelab: CPU Usage - 0.2s system + 1.2s user = 1.4s total (3.6s, 38.2% cpu)
    irun: *E,ELBERR: Error during elaboration (status 1), exiting.

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