I have a Testbench with a DUT which has VHDL and Verilog RTL modules. The tb_top is verilog. The test file is a verilog.
From the verilog test, I need to force a signal inside the DUT several hierarchies down.
The signal I need to force is inside a VHDL module. This signal is not available at the top level.
How do I do it?
I am using ncverilog/ncvhdl/irun version of 9.2.
Any suggestions with some simple code example is going to be very helpful.
I was able to source to the signal of interest, but i have a requirement to keep giving different values to that signal of interest.
I tried something like this, which din't work out.
$nc_force("source", "reg") ;
reg = reg+1'b1;
The reg value in my simulation keeps incrementing but the source signal of interest does not increment.
Is there any other way to perform the same kind of operation??