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How to short the time during ncelab when do gate level simulation

zlzg12345
Hi all,

For our huge netlist, it takes so long do the ncelab each time though we only modify  a few “force signal" code .We have compile the  netlist and testbench into the different library. Is there anyway to short  the time during ncelab ?

Thanks.
Parents

  • In the current release of IUS10.2, there is a new capability called “Multi-Snapshot Incremental Elaboration”. This might be useful for your situation in that you would only have to re-elaborate the snapshot for the testbench while not having to re-elaborate  the snapshot for the DUT.

    FYI, this does require the Incisive Advanced Option license to run.

    Tim

Reply

  • In the current release of IUS10.2, there is a new capability called “Multi-Snapshot Incremental Elaboration”. This might be useful for your situation in that you would only have to re-elaborate the snapshot for the testbench while not having to re-elaborate  the snapshot for the DUT.

    FYI, this does require the Incisive Advanced Option license to run.

    Tim

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