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Enabling System Verilog Assertions with irun

samk

 I have written a module which contains SV assertions:

`define ASSERT_ON
`define COVER_ON

module dsp_tmr_sva (reset_n);
input reset_n;
.
<SV Assertions>
.
.
I instantiated the above module in the top level TB. I am using Cadence tools.
What else do I need to do in order to fire the assertions with the irun command.

  • Don't let the `defines fool anyone.

    Because SVA is part of the language, you don't have to do anything special to enable them.  You just have to tell your particular simulation that you want to created a coverage database, and specify what type of coverage data you want to put in it.

    irun -coverage F

    or

    ncelab  -coverage F

    This will create the coverage database upon exit.  Then to view the coverage use the IMC tool (execute linux: imc -gui) and load up the coverage database.

     

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