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Gate level Simulation

Mandate

Hi All,

I am using Candence IES tool, and also new to cadence tools.

What are the inputs required for GATE level simulation (after synthesis)?

I have standard library file in .v format and .v netlist. Is this enough for gate level simulation?

Please help me in this

Thanks, Sam

Parents

  •  Hi Tim,

    With testbench I tried simulatiing the synthesiszed netlist without SDF file. It gave approximately 0.7ns clock to q delay. I think, it is taking only the gate delay from the standard cell library and It doesn't have the net or path delay.

    Would like to know whether my understanding is correct?

    Is SDF file output of synthesis process -  Cadence Encounter(R) RTL Compiler ?

    Very much appreciate your reply

    Thanks,

    Sam

Reply

  •  Hi Tim,

    With testbench I tried simulatiing the synthesiszed netlist without SDF file. It gave approximately 0.7ns clock to q delay. I think, it is taking only the gate delay from the standard cell library and It doesn't have the net or path delay.

    Would like to know whether my understanding is correct?

    Is SDF file output of synthesis process -  Cadence Encounter(R) RTL Compiler ?

    Very much appreciate your reply

    Thanks,

    Sam

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