Simple UVM Bench Issue

I have created a UVM Bench.  I am using INCISIVE_10_20.

All components are in place and things are going good.  

I have the following:

(1) Master Agent

(2) Driver

(3) Monitor

(4) Sequencer

(5) test_lib : I specify the particular sequence to use in each testclass

(6) Scoreboard 

My Driver is driving the intended interface signals.  No problems.

But, I want to do something very simple now.  

There is a signal which the Driver drives into the DUT, which I have currently coded such that it randomly toggles.

I want to set a switch from a test (say, class myTest_x) in the test_lib, such that my Driver drives this signal either randomly (as coded now) or keeps it fixed (say, always high).

So, in the Driver, part my code should be as follows:

  virtual task run();
    fork
      get_and_drive();
      reset_signals();
      drive_sig_X() ;
    join
  endtask : run

  virtual protected task drive_sig_X();
    @(posedge h_intf.sig_sysreset);
    forever begin

       @(posedge h_intf.sig_sysclk);
        begin
          if (switch_from_testClass == 1)      <----  How do I set this switch from the myTest_x in test_lib
          begin
           if ($urandom % 2)
               h_intf.sig_X <= 1'b0 ;   // random low
           else
               h_intf.sig_X <= 1'b1 ;   // random high
          end
          else                                // if the switch is zero
               h_intf.sig_X <= 1'b1 ;      // keep it always high
        end

    end
  endtask : drive_sig_X 

 Thanks,

 Ashfaq Hossain