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reg : vhdl design with systemverilog testbench

Hi Everyone,

Could someone help me in verifying "vhdl" design using systemverilog testbench , i am using INCISIVE 10.20.026 as "irun sample.vhd tb_sample.sv" and it is giving the following error

" ASSERT/WARNING (time 0 FS) from package ieee.STD_LOGIC_ARITH, this builtin function called from process tb.c1:$PROCESS_000 (architecture worklib.sample:behv)
Built-in function result set to 'X' due to a ('U', 'X', 'W', 'Z', '-') in an operand."

So anyone please help me in verifying the design

Thanks in Advance

With regards

Srikanth M.

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