Timing checks in ncsim

HI!

I am new to using ncsim and all so please excuse for simplistic questions, so anyways I want to simulate a state machine made up of DFFs (with no reset) and some logic gates. When I try to simluate the design electronically everything works fine but if use verilog descriptions of standard library cells (provided by the vendor) I get these X all along as everything connected to the DFFs has an X state.

Is there any way to feed all the nodes some crap data (that is ofrced on them for like 10 clock periods and then deasserted)?

My second question, is there anyway of disabling timing checks using ncsim. I am using ams simulator from ADE in cadence IC6.15. I already tried the option simulation->options->ams simulator->timing-> No timing checks but that doesn't help.