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  3. Unwanted "X" coming during re-simulation with vector

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Unwanted "X" coming during re-simulation with vector

dhanash
dhanash over 13 years ago

Hi,

We are creating vectors with vcd files. If we re-run the simulation we are seeing few "X" on the signals which in turn causing simulation fail.

Location of signal going "X" is,

At the synchronizer input we are seeing logic high input for two clocks, for the first cycle synchonizer is able to give correct output but for second clock instead of giving logic high output we are getting X .

 

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