help needed on the use Scemi2.0 Pipe between OVM tb and HDL

Hello, 

  I want to use the scemi2.0 pipe to connect a ovm TB with a RTL DUT.  In ovm side, I use the ovm_accel_pkg. I made an every simple example, in which a ovm_accel_input_pipe_proxy is used in the tb side and a scemi_input_pipe is used in the DUT side. But when I try to run the compiled snapshot, some mistakes show up like 

     Error: marg_deposit_handle: can't find top_m.dut_i.receive_pipe.fp_elements_count
     Error: marg_value_handle: can't find top_m.dut_i.receive_pipe.fp_read_pending
     Error: top_m.dut_i.receive_pipe.fp_buffer is not a Verilog memory
     Initialization ERROR !!!  port top_m.dut_i.receive_pipe TBA_callback occurred but is not initialized, exiting simulation ...

The Makefile I used to compile is : 

  1 c_inc_dir=-I/proj/asic/tools/cadence/uxe/11.1.1_latest/tools/gift/ovm_accel/src/c \
  2         -I/proj/asic/tools/cadence/uxe/11.1.1_latest/tools.lnx86/etc/tba \
  3         -I/proj/asic/tools/cadence/uxe/11.1.1_latest/tools.lnx86/include \
  4         -I/proj/asic/tools/cadence/incisive/INCISIV_11.10.010/tools.lnx86/include
  5
  6 SRCFILE=top_m.sv \
  7         -incdir .
  8
  9
 10 C_FILE=/proj/asic/tools/cadence/uxe/11.1.1_latest/tools.lnx86/etc/tba/uatba_event.cpp \
 11        /proj/asic/tools/cadence/uxe/11.1.1_latest/tools.lnx86/etc/tba/uatba_scemi.c \
 12        /proj/asic/tools/cadence/uxe/11.1.1_latest/tools.lnx86/lib/libuatba_dc.so
 13
 14
 15 SCEMI_PIPE=/proj/asic/tools/cadence/uxe/11.1.1_latest/tools.lnx86/etc/tba/uatba_event.sv \
 16            /proj/asic/tools/cadence/uxe/11.1.1_latest/tools.lnx86/etc/tba/uatba_sv.sv \
 17            -incdir /proj/asic/tools/cadence/uxe/11.1.0_latest/share/uxe/etc/tba \
 18            -v /proj/asic/tools/cadence/uxe/11.1.0_latest/share/uxe/etc/tba/scemi_pipe.vp
 19 ## -y /proj/asic/tools/cadence/uxe/11.1.0_latest/share/uxe/etc/tba +libext+.v+.vp+.sv
 20 ##-incdir /proj/asic/tools/cadence/uxe/11.1.0_latest/share/uxe/etc/tba \
 21
 22 OVM_ACCEL=/proj/asic/tools/cadence/uxe/11.1.1_latest/tools/gift/ovm_accel/src/sv/ovm_accel_pkg.sv \
 23           -incdir /proj/asic/tools/cadence/uxe/11.1.1_latest/tools/gift/ovm_accel/src/sv \
 24           /proj/asic/tools/cadence/uxe/11.1.1_latest/tools/gift/ovm_accel/src/c/ovm_accel_pipe_if.cpp
 25
 26 IRUN_OPT= -DNO_IXCOM -top uatba_event -top top_m  -ovm -sv -dpi -access +rwc -timescale 1ns/1ns +defineall+NO_IXCOM -c
 27
 28 compile:
 29         irun $(IRUN_OPT) $(OVM_ACCEL) $(SRCFILE) $(c_inc_dir) $(C_FILE) $(SCEMI_PIPE)

The errors shown above are related to the marg C interface. I guess I did not explicitly specify it. And the 'fp' of 'fp_elements_count' seems to stand for fast pipe. Again, I did not use fast pipe in my example. How can it complain about the fast pipe? I really don't understand.

Is there anyone can tell me where I made mistakes and how to solve it ? Thanks a lot !  I list my codes below. 

 Thanks and best regards, 

Xinwei 

 My code is : 

tb.sv :

  1 import ovm_pkg::*;
  2 import ovm_accel_pkg::*;
  3 `include "ovm_macros.svh"
  4 class data_tran_t extends ovm_object;
  5     reg[7:0] data;
  6     `ovm_object_utils_begin(data_tran_t)
  7         `ovm_field_int(data,OVM_ALL_ON)
  8      `ovm_object_utils_end
  9
 10     function new(string name ="unamed_data_tran_t");
 11         super.new(name);
 12         data=8'hff; // default value for data
 13     endfunction
 14
 15     function void set(int unsigned value);
 16         ovm_report_info(get_type_name(), $sformatf("data is set to  %h",value));
 17         data=value;
 18     endfunction: set
 19 endclass
 20
 21 class tb extends ovm_component;
 22     data_tran_t transaction;
 23     ovm_accel_input_pipe_proxy#(data_tran_t) send_pipe;
 24     `ovm_component_utils_begin(tb)
 25         `ovm_field_object(transaction, OVM_ALL_ON)
 26     `ovm_component_utils_end
 27
 28     function new(string name="unamed_tb", ovm_component parent=null);
 29         super.new(name,parent);
 30         transaction=new("transaction");
 31     endfunction: new
 32
 33     function void build();
 34         super.build();
 35         set_config_string("send_pipe","hdl_path","top_m.dut_i.receive_pipe");
 36         send_pipe=new("send_pipe", this);
 37         send_pipe.set_pipe_name("top_m.dut_i.receive_pipe");
 38
 39     endfunction:build
 40
 41     task run();
 42         transaction.set(20);
 43         send_pipe.put(transaction);
 44     endtask
 45
 46 endclass

dut.sv : 

  1 module dut;
  2 scemi_input_pipe#(1,1) receive_pipe();
  3 reg [7:0] rec_data;
  4 integer numRead;
  5 bit eom;
  6    
  7 initial begin
  8     
  9     forever begin
 10         receive_pipe.receive(1,numRead,rec_data,eom);
 11         $display("numRead:  %d", numRead);
 12         $display("recdata:  %h", rec_data);
 13         $display("eom:      %d", eom);
 14     end//forever loop
 15 end//initial
 16 endmodule

top_m.sv 

  1 `include "tb.sv"
  2 `include "dut.sv"
  3 module top_m;
  4     tb tb_i=new("tb_i");
  5     dut dut_i();
  6    
  7    initial begin
  8     run_test();
  9    end
 10 endmodule